1. Field of the Invention
The present invention relates to measures against a freeze and improvement in noise tolerance in an IIC communication system.
2. Description of Related Art
An IIC (Inter-Integrated Circuit) bus communication has been known as a communication method using a bi-directional bus including two wires, which is applied for controlling efficiently devices integrated in household equipment (such as television sets, radio sets and DVD recorders), communication equipment (such as mobile phones and personal computers) or industrial equipment. IIC bus specification is defined in, for example, “THE I2C-BUS SPECIFICATION”, VERSION 2.1, JANUARY 2000.
By using such an IIC bus communication, the system control can be composed of only two bus lines including a serial data (SDA) line and a serial clock (SCL) line. Moreover, since addressing and data-transmission format and devices are defined in the IIC specification, system definition by the use of software is available, and the addition/removal of IC in the system can be performed in a simple manner. Every device connected to the bus has its own unique address and it operates as a transmitter or a receiver in accordance with the function of the equipment, and data can be transmitted between the respective devices.
A relationship as a master device and a slave device is established constantly between the respective devices, and the master device functions as a master transmitter or a master receiver. The master device denotes a device for starting data transmission on a bus, and it generates a clock signal for enabling the transmission. A device that is addressed at that time by the master device becomes a slave device. The length of each byte outputted to the SDA line is 8 bits. The number of bytes that can be sent at one transmission is not limited particularly. An acknowledge bit is required after each byte. A clock pulse for the acknowledge bit is generated by the master device. When such an acknowledge clock pulse is generated, the transmitter opens the SDA line. The receiver is required to make the SDA line “L” in accordance with the output of the acknowledge clock pulse so that the SDA line is stabilized in the “L” state when the acknowledge clock pulse is in the “H” state.
The IIC bus functions as a multi-master bus where multiple master devices can control a bus simultaneously, and it is expected to be predominant, corresponding to the future trend of higher function of a set and more complicated systems. The fact that multiple master devices can be connected to the IIC bus implies that the multiple master devices may start data transmission simultaneously. For preventing occurrence of such a phenomenon, the IIC bus and all of the IIC bus interfaces are wired-AND-connected. In a case where multiple master devices try to send information to the bus, a master device, which generates ‘1’ first when the other master device generates ‘0’, is disabled to perform a communication. The following description refers to a bit error that occurs at the time of the IIC bus communication.
FIG. 6A is a diagram showing a configuration of a conventional IIC bus system including two master devices. In this system, a first master device 3, a second master device 4, a first slave device 5 and a second slave device 6 are connected in parallel to bus lines including a SCL line 1 and a SDA line 2. In addition, one terminal of a SCL line pullup resistor 7 and one terminal of a SDA line pullup resistor 8 are connected to the SCL line 1 and the SDA line 2 respectively, while the other terminals of the pullup resistors 7, 8 are connected to a power source 9.
FIG. 6B(a) shows waveforms of SCL and SDA during a normal communication in this IIC bus system. The clock pulses S7-S0 in the SCL correspond to respective bits of 1-byte data, and ‘A’ denotes an acknowledge clock pulse. When the acknowledge clock pulse is in the “H” state, the SDA line is in the “L” state.
FIG. 6B(b) shows a waveform of a state where an acknowledge signal shifts by 1 bit and the communication freezes. This can occur, for example, as a result of the first slave device 5 causing a bit error under the influence of external noise or the like during receiving a slave address at the time that the first master device 3 acquires continuously the read-data from the first slave device 5. As a result, for example, in a case of returning the acknowledge pulse earlier by 1 bit in comparison with the acknowledge bit, the slave device sets the SDA as “L” while the first master device 3 sends the eighth bit of the slave address as “H”. The first master device 3 recognizes this phenomenon as the second master device 4 trying to start data transmission, and stops supplying of a clock to the SCL line 1. As a result, since the clock is not supplied to the SCL line 1, the SDA line 2 is pulled to “L” by the first slave device 5, and the IIC bus communication will freeze.
JP2003-308257 A describes an example of techniques for coping with abnormal communications in an IIC bus communication system. The technique described in JP2003-308257 A relates to a method for preventing a malfunction or a runaway of a slave device when resuming the communication after interruption of the communication due to the occurrence of an abnormality such as a power failure. However, the method cannot be applied to cope with a problem as mentioned above, that is, a freeze of the IIC bus communication under the influence of external noise or the like.
FIG. 7 is a block diagram showing the interior of the first slave device 5. FIG. 7 shows only parts relating to processing the SCL signal inputted through a SCL input terminal 10, but parts relating to processing SDA signal are omitted in the figure.
The SCL signal is decoded at an IIC decoding circuit 12 via a comparator 11a in the first slave device 5. For the reference voltage of the comparator 11a, an output voltage of a reference voltage circuit 13 is supplied via a buffer circuit 14. The output voltage of the reference voltage circuit 13 via the buffer circuit 14 is supplied also to the IIC decoding circuit 12.
The following factors can be considered as causing a shift of the acknowledge signal in the circuit of the first slave device 5:                (1) external noise is superimposed on the SCL line 1;        (2) noise is superimposed on the reference voltage side of the comparator 11a; and        (3) noise is superimposed on the output of the comparator 11a.         
When the first slave device 5 returns an acknowledge signal for an incorrect bit due to the influences of external noises or the like as mentioned above, a freeze of the IIC bus communication is apt to be caused.